;******************************************************************************* ; Super System Card 3.0 for MC-Genjin ;******************************************************************************* ; These are all modified versions of NEC / Hudson Soft's CD System Card 3.0 ; software to support extended memory. This can be used in translations or the ; development of completely new software. ; ; Version 3.x targets a 512KB ROM + 512KB RAM MC-Genjin Card ; It can also be run in Mednafen. $00000 - $7FFFF is the System Card ROM, ; while $80000 - $FFFFF is all RAM. ; ; Version 4.x targets the CD Stupid Card (512KB ROM + 2MB RAM) ; This card has several new operating modes, but is fully compatible with the ; setup used for 3.x above. ; ; All of these use the Japanese System Card 3.0 as a base. ; MD5 == 38179DF8F4AC870017DB21EBCBF53114 ; ; For both targets the System Card ROM is padded to 512KB. You're welcome to ; place any of your own development or diagnostic routines in the upper 256KB ; as it's completely empty. ; _/ 2015-10-27 + Super System Card, DERP v3.6 + Stupid System Card, DERP v4.1 Apparently the Duo and other consoles with an internal Super CD 3.0 don't honor the CARDn pin to disable their internal SuperCD RAM. EX_MEMOPEN is called directly @286B, and the write sequence to $1850 right after enables the RAM itself. EX_MEMOPEN now routes to our dummy function outright, and the writes to $1850 have been NOP'd out. _/ 2015-05-09 + Stupid System Card, DERP v4.0s Found an issue with the TurboGrafx-16's RESETn line taking so long to rise that the CPU has already begun executing while it's still low. Because the MC-Genjin CD requires RESETn to rise before its registers can be altered, the CD-Stupid Card now has an additional delay during startup. _/ 2015-03-02 + Super System Card, DERP v3.5 + Stupid System Card, DERP v4.0 Added MC-Genjin Header and multiregion startup code. EX_MEMOPEN @ $E0DE in the BIOS jump table now points to $FF50 instead of $FE92. The dummy subroutine at $FF50 always returns with X = $03, A = $68, and CLC. ; EX_MEMOPEN and Friends ;------------------------------------------------------------------------------- ; The SuperCD RAM requires both an authentication and unlock step before use. ; ; Since this memory is included in all Duo consoles but doesn't honor the CARDn ; pin's state to disable itself, we need to get rid of all these sequences ; in order to prevent a possible bus fight. ; @00DE in ROM E0DE jmp $FE92 ; EX_MEMOPEN, Changed to $FF50 @1E92 in ROM FE92 / EXMEMOPEN jmp $FF50 ; Removed original function, see below for ; the fixed version... @1F50 in ROM (NEW) LDA #$68 LDX #$03 clc rts ; A = $68, X = $03, CLC ; These pass, but will cause any duplicates of the @286B in ROM ; routine below to skip the RAM unlock. ; (MSB of X is CLEAR) C86B jsr $FE92 ; (C = Has RAM, A = RAM Start Bank, X = Version ???) bcs $C88C ; I wonder if the MSB of X indicates whether or not ; the Super CD RAM has already been unlocked. TXA BIT #$80 beq $C87F ; Why not just TXA, BPL? Whatever... LDA #$AA ; ! STA $18C0 ; ! LDA #$55 ; <- This enables the Super CD RAM, which may cause STA $18C0 ; a bus fight if this is a Duo... NOP'd out. C87F ... C88C ... ; Startup Patch ;------------------------------------------------------------------------------- ; Note that the stall here is needed since machines like the TurboGrafx-16 have ; an obnoxious RESETn rise time on the HuCard Slot. If this is not done, the ; region write to the mapper could be lost. ; ; Strangely, this is not an issue on the PC-Engine. ; ; Anyway, the startup routine has been modified as follows so that there are ; two reset vectors, one at $FF0F (NATIVE) and $FFF0 (SWAPPED). ; ; The NATIVE vector performs all initialization, then jumps to $FF20. ; The SWAPPED vector immediately jumps to $FF60, performs its initialization, ; then jumps to $FF20. ; ; Version 3.x is mostly the same as this, minus the delay and plus a write ; to MC-Genjin in order to map in the second 256KB page. The addresses are a ; little different, too. ; @1Fxx in ROM ; Native Swapped sei ; 78 1e jmp $FF60 ; 4c 60 ff 32 06 ff ... FF60 cla ; 62 46 tax ; aa 55 tay ; a8 15 dex ; ca 53 txs ; 9a 59 cld ; d8 1b .wait dex ; ca 53 bne .wait ; d0 fd 0b bf dey ; 88 11 bne .wait ; d0 fa 0b 5f LDA #$FF ; a9 ff 95 ff STA $FFFE ; 8d fe ff b1 7f ff jmp $FF20 ; 4c 20 ff 4c 20 ff ... FF20 cla ; 62 jmp $E0F3 ; 4c f3 e0