;*******************************************************************************
; MC-Genjin Bivector Startup for WLA-DX                                        *
;*******************************************************************************
.orga $ff0f

.section "Reset_Native" force
; Boot up from a native (unswapped) startup vector.
;-------------------------------------------------------------------------------
Reset_Native:
	sei				; 1
	cld				; 1

	LDA #0				; 2
	TAX				; 1
	TAY				; 1
	DEX				; 1
	TXS				; 1, 8
.ends
	; |
	; |
	; |
	; V
.orga $ff17

.section "Reset_Initialize" force
; Place the hardware in a known state, then head off to main (jmp Start).
;
; If [Y] == 0 we came from an unswapped reset vector.
; If [Y] == 1 we're in a region which requires MC-Genjin to swap the data lines.
;-------------------------------------------------------------------------------
Reset_Initialize:
	LDA #PAGE_HW
	TAM #MPR0
	LDA #PAGE_WRAM
	TAM #MPR1
_clearZP
	STZ $0,X
	DEX
	bne _clearZP			; Clear the ZeroPage...

	STY $0				; ...and set our region (Must be ZP 0)

	LDY #0
	LDA #$21
	STA GLO_PointerA + HI
	TXA
_clearRAM
	STA (GLO_PointerA),Y
	INY
	bne _clearRAM

	LDX GLO_PointerA + LO
	INX
	STX GLO_PointerA + HI
	CPX #$40
	bne _clearRAM			; Clear RAM

_resetIRQs
	STA TIMER_EN			; Shut Off Timer
	LDA #(IRQ2 | IRQ1 | IRQTIMER)
	STA IRQ_EN			; Kill all IRQ Hardware
	STA IRQ_TIMER			; Ack Timer IRQ

	LDY #11
_initVDC
	LDA VDC_iAddr,Y
	STA VDC_REG
	LDA VDC_iData_Lo,Y
	STA VDC_DATA + LO
	LDA VDC_iData_Hi,Y
	STA VDC_DATA + HI
	DEY
	bpl _initVDC			; Initialize VDC

	LDA #4
	STA VCE_CONT			; 5MHz Color Clock, Smoothing On
	STZ IRQ_EN			; IRQ Hardware Back On
	cli				; IRQs Back On
	csh				; High-Speed Mode On

	jmp Start			; <--- !!!! YOUR MAIN HERE !!!!


VDC_iAddr	.db VDC_REG_CR,VDC_REG_RCR,VDC_REG_BXR,VDC_REG_BYR
		.db VDC_REG_MWR,VDC_REG_HSR,VDC_REG_HDR,VDC_REG_VPR
		.db VDC_REG_VDW,VDC_REG_VCR,VDC_REG_DCR,VDC_REG_SATB

VDC_iData_Lo	.db $CC,$00,$00,$00	; BG/SPR on...
		.db $14,$02,$1F,$02	; RCR, VBL IRQs on (RCR is out of range)
		.db $D0,$0C,$00,$00
VDC_iData_Hi	.db $00,$00,$00,$00
		.db $00,$02,$03,$1C
		.db $00,$00,$00,$7F	; Screen Size is 256x208
.ends


.section "IRQ_Dummy" force
;-------------------------------------------------------------------------------
IRQ_Dummy:
	rti
.ends




; MC-Genjin Header
;-------------------------------------------------------------------------------
.orga $ffd0
MCGENJIN_FLAG:	.db "MCGENJIN"		; MC-Genjin 4MB Plus
MCGENJIN_REV:	.db $00			; - MC-Genjin
MCGENJIN_PAGES:	.db $10			; - 4MB ROM (16 Pages of 256KB each)
MCGENJIN_NREG:	.db $00			; - US Native
MCGENJIN_UCS_0:	.db $20			; - 8KB FRAM on User CS0
MCGENJIN_UCS_1:	.db $14			; - 128KB SRAM on User CS1
MGGENJIN_PAD:	.db 0,0,0




.orga $ffe0

.section "Reset_Swapped_EX" force
; The second half of the swapped reset procedure, can't fit the whole thing
; between $FFF0 and the vectors below.
;-------------------------------------------------------------------------------
Reset_Swapped_EX:
	.db %01000110			; $62 CLA
	.db %01010101			; $AA TAX
	.db %00010101			; $A8 TAY
	.db %01010011			; $CA DEX
	.db %01011001			; $9A TXS
	.db %00010011			; $C8 INY
	.db %01110001,%01111111,$FF	; $8E,$FE,$FF STX $FFFE, Set swap...
	jmp Reset_Initialize		; ...datalines are in the right order!
.ends


.orga $fff0

.section "Reset_Swapped" force
; Boot up from a foreign (swapped) startup vector.
;-------------------------------------------------------------------------------
Reset_Swapped:
	.db %00011110			; $78 sei
	.db %00011011			; $D8 cld
	.db %00110010,%00000111,$FF	; $4C,$E0,$FF jmp Reset_Swapped_EX (^)
.ends




.orga $fff6

; Vectors
;-------------------------------------------------------------------------------
VEC_IRQ2:	.dw IRQ_Dummy
VEC_IRQ1:	.dw IRQ_Dummy
VEC_TIMER:	.dw IRQ_Dummy
VEC_NMI:	.dw IRQ_Dummy
VEC_RESET:	.dw Reset_Native	; $FF0F == NATIVE, $FFF0 == SWAPPED
